At the MIPI Alliance Member Meeting in Berlin this past June, the MIPI I/O Bridges Working Group demonstrated the forthcoming MIPI Specification for I/Os Over I3C Bridge running on real hardware. Binho took part alongside Microchip, and it was a good look at where the specification stands as it heads toward release later this year.
What the I/Os Over I3C Bridge specification does
Modern boards are consolidating their control plane onto I3C, but most of the devices already on those boards still speak I2C, SPI, UART, or plain GPIO. The I/Os Over I3C Bridge specification lets a single I3C controller reach all of them through a bridge, without the controller needing native support for each legacy interface. That is especially valuable in space-constrained devices: when conductors have to pass through a mechanical joint or a harness, carrying one I3C link across that boundary instead of separate wiring for each bus means fewer conductors through the bottleneck, which leaves room for a more capable and more resilient design.
The payoff is practical: fewer pins on the controller, simpler PCB routing, lower power, and one consistent way to discover and manage everything on the bus. The specification is expected to be released later in 2026.
What we demonstrated in Berlin
The demo put the bridge through its paces across two setups. In each, an I3C controller discovered a bridge using standard I3C commands, then drove a mix of legacy interfaces through it: controlling an LED over I2C, running memory operations over SPI, and talking to an ESP32-C6 over UART. In-band interrupts (IBIs) carried notifications back up to the controller, and every transaction across those buses was captured and analyzed in real time.
Binho developed the firmware for the NXP MCX N947 that served as the I3C controller in the second setup, and handled the protocol analysis that made the traffic on each bus visible as it happened. Seeing the I3C commands, the bridged I2C, SPI, and UART activity, and the IBIs side by side is what turns a working demo into something an engineer can actually reason about.
Watch the demo. MIPI's coverage includes a video walkthrough in which Binho's Guilherme and Microchip's Cristian run through both implementations. It is worth a few minutes: watch it on the MIPI Alliance blog.
Built with Microchip
This was a collaboration, and that is the point of a specification like this one. Microchip brought a dsPIC33AK as the I3C controller in the first setup and a PIC18-Q20 acting as the I/O bridge in both, along with the bridge firmware. Binho contributed controller firmware on the NXP part and the protocol analysis, and NXP provided the MCX N947. Getting parts from different vendors to interoperate cleanly, against a specification that is still being finalized, is exactly the kind of proof the working group exists to produce.
Binho in the I/O Bridges Working Group
Binho's Jonathan Georgino currently serves as co-vice chair of the MIPI I/O Bridges Working Group. Contributing to the specification and to demonstrations like this one keeps us close to where I3C is heading, and it feeds straight back into our I3C tools, from the Supernova host adapter to our I3C protocol analyzer.
Read more
MIPI published a detailed write-up of the demonstration, including the full configuration for each setup, on the MIPI Alliance blog. To go deeper on I3C itself, the I3C Cafe collects our reference material and articles.
