// application note
AN0009 Managing a CMIS optical module over I3C with the Binho Supernova
The OSFP-XD connector already permits I3C single data rate at 12.5 Mbit/s on the same two pins that carry the required 400 kbit/s I2C, and silicon vendors are shipping CMIS targets that use it. No published revision of CMIS specifies an I3C management interface, so a host driving one is following a private derivation rather than a standard. This application note brings up a CMIS module over I3C single data rate from a Binho Supernova, separates what carries over from the I2C binding unchanged from what is a genuine upgrade and what is not specified at all, and supplies a command that establishes which of two incompatible address wrap rules a given target implements.
- Products
- Binho Supernova
- Protocols
- I3C
- Topics
- CMIS
- Revision
- Rev 1.0 · November 6, 2026
// outcomes
What you'll walk away with
By the end of this document a reader with the hardware in front of them will have brought an I3C CMIS target onto a bus by dynamic address assignment, read its identity and validated its Page 00h checksum over I3C single data rate private transfers, established which address roll-over rule it implements, and received an in-band interrupt from it with no interrupt pin connected.
The document covers a level A binding, meaning I2CMCI semantics preserved byte for byte over I3C private transfers, which is what NXP shipped and what will exist in laboratories for the next two years. A native I3CMCI adopting SPIMCI's three dimensional addressing and large transfers is discussed in Section 4 but is not implemented here, because it requires OIF work that has not happened.
AN0008 covers the register model itself and is a prerequisite. This document assumes it.
// background
Background
The connector already allows it. OSFP-XD Revision 1.1 section 10.5.1 lists optional I3C single data rate at 12.5 Mbit/s on the same SCL and SDA pins that carry the required 400 kbit/s I2C. An I3C managed module is legal at the connector today.
Silicon vendors are already building to it. NXP application note AN15071 ships a working CMIS 5.3 target over I3C on the MCX N947 at 12.5 Mbit/s. To exercise it, NXP wrote USB-to-I3C bridge firmware for a second development board and a bespoke host executable, which is the gap this note fills with a shipping adapter.
What does not exist is a specification saying what correct looks like. This note is therefore as much about the decisions an I3C binding forces as about the procedure, because a reader adopting one has to make those decisions and write them down.
// applicable devices
Applicable devices
| Item | Role | Basis |
|---|---|---|
| Binho Supernova | Host adapter, I3C controller | Section 9, every command in Section 6 |
| NXP FRDM-MCXN947 running the Binho CMIS target firmware | I3C CMIS target | Section 9, enumeration through checksum |
| NXP MCX N947 running AN15071 firmware | I3C CMIS target | Not exercised for this note |
| Any I3C CMIS target at static address 0x50 | Target | Not exercised for this note |
The Binho Pulsar has no I3C interface. This note requires a Supernova. The utility refuses
--transport i3con a Pulsar rather than failing later in a way that looks like a wiring fault.
The rows marked as not exercised are not claims. The mapping in Section 4 is derived from OIF-CMIS-05.3 and 05.4, from MIPI I3C Basic v1.1.1, and from OSFP-XD Revision 1.1. Section 9 reports what we ran and against what. We have not run this note against a commercial optical module, and no result here should be read as one.
// what's covered
What's covered in the note
- 01 Introduction
- 02 Required equipment and software
- 03 Two levels of binding, and which one you are building
- 04 The mapping, mechanism by mechanism
- 05 Every CMIS module answers at 0x50
- 06 Procedure
- 07 The in-band interrupt is the part worth building for
- 08 What the analyzer adds
- 09 Measured results
- 10 Troubleshooting
The full procedure, measured results, and reference code are in the PDF and the assets archive.
// materials
What you'll need
Binho Supernova USB host adapter for I3C, I2C, SPI & UART View product // our edge
We don't just follow the I3C spec.
We don't watch from the sidelines. Plugfest after plugfest, our team is in the room where vendor I3C implementations come together — finding edge cases, debugging quirks, and validating real silicon against the spec.
// track record
We've been doing this for years.
Long enough to know where the gotchas live.
// 01 · standards
We help write the spec.
Binho is a MIPI Alliance Contributor Member, actively shaping I3C — a foundational protocol for cutting-edge embedded systems.
// 02 · tools
We build the tools.
200+ semiconductor companies use Binho tools to develop, validate, and ship devices with I3C protocol support.
// 03 · plugfests
We prove it in the field.
We've verified our tools at the past 5 MIPI I3C Plugfests — and helped others verify theirs too.
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Put it on the bench
Every step in AN0009 was run on the Binho Supernova. Get the hardware to reproduce it, or talk to our engineers about your I3C bring-up.