// DDR5 SPD over I3C
Bring up and debug
DDR5 SPD over I3C.
DDR5 moved the SPD, thermal, and power sideband onto MIPI I3C Basic, with an SPD5 Hub on each module. Binho gives you the tools to bring it up, decode the full sideband, and debug what breaks.
// the ddr5 sideband
DDR4 used SMBus. DDR5 uses I3C.
Each DDR5 module carries a Serial Presence Detect device that tells the system what the memory is and how to run it. In DDR4 the host read it over an SMBus derived from I2C. DDR5 replaced that bus with a MIPI I3C Basic sideband, standardized by JEDEC as the Module Sideband Bus (JESD403).
The reason is load and speed. A fully loaded DDR5 DIMM puts around 40 devices on the sideband, and the memory controller has to reach them without slowing boot. I3C Basic answers with up to 12.5 MHz instead of 1 MHz, dynamic address assignment, in-band interrupts for thermal and power alerts, and CCCs like SETHID and SETAASA for fast enumeration, while staying backward compatible with I2C. The SPD5 Hub (JESD300-5) is the device that makes it work on each module.
// the sideband
One controller. One hub per DIMM.
A read of the SPD, a temperature poll, a PMIC register: each one starts at the host controller, crosses the I3C sideband, and passes through the SPD Hub to a device on the module's local bus.
// module sideband bus
The I3C host sideband
A single controller, the memory controller or your test host, drives the module sideband bus. I3C Basic runs it at up to 12.5 MHz, with dynamic address assignment, in-band interrupts for thermal and power alerts, and backward compatibility with legacy I2C at 1 MHz.
// the bridge on each dimm
The SPD5 Hub
Each DDR5 module carries an SPD5 Hub. It bridges the host sideband to a local I2C bus and isolates that local load from the host, so a fully loaded DIMM can keep roughly 40 endpoints answering at speed. This is the device JESD300-5 defines.
// devices behind the hub
SPD, thermal, and power
Behind the hub sit the devices a platform actually reads: the SPD EEPROM with the module parameters, the on-DIMM temperature sensor, the PMIC, and the registering clock driver. Each carries its own JEDEC standard.
// solutions
See the sideband. Then drive it.
One tool decodes the DDR5 SPD sideband down to the wire. The other reads and programs it as the host controller.
Software · Saleae Plugin
I3C Protocol Analyzer Plugin
The whole sideband, decoded.
Decodes the DDR5 module sideband down to I3C Basic timing, CCCs, IBIs, and PEC, and labels the JESD300-5 SPD and hub transactions, inside the Saleae tool your engineers already use. When a DIMM will not enumerate, you can see exactly where it stops.
- I3C Basic timing: DAA, CCCs, IBI, PEC
- JESD300-5 SPD and hub transaction decode
- Full I3C spec coverage: v1.0, v1.1, v1.1.1, v1.2
Hardware · USB Host Adapter
Binho Supernova
Be the memory controller.
The Supernova drives the DDR5 sideband as the I3C host controller, fully scriptable from Python and C. Read and program the SPD EEPROM, enumerate the SPD Hub, and poll the on-DIMM temperature sensor and PMIC, straight from your laptop or a regression rig.
- Operates as I3C Controller or Target
- Read / program SPD, poll temp sensor and PMIC
- I3C Basic · I2C · GUI · Python · C/C++ SDK
// our edge
The DDR5 sideband is I3C at heart.
We don't watch from the sidelines. Plugfest after plugfest, our team is in the room where vendor I3C implementations come together: finding edge cases, debugging quirks, and validating real silicon against the spec.
// collaborations
Beyond the tools.
Our work lives inside the I3C industry's dev kits, app notes, and demos.
Bundled with the PIC18-Q20 Curiosity Nano.
As an official Microchip Development Tool Partner, we ship our I3C Protocol Analyzer plugin for Saleae Logic with every PIC18-Q20 Curiosity Nano dev kit. Microchip's lowest-cost I3C Target MCU board includes a free 45-day license, bundled directly with the hardware.
Read the announcement
Featured in their I3C application note.
AN5879, "Introduction to I3C for STM32H5 series MCU," is the 64-page document STMicro hands to every developer adopting I3C on STM32. The decoded I3C waveforms throughout the document are captures from our protocol analyzer.
View AN5879 (PDF) Powering their live I3C demo.
Microchip Try runs an interactive I3C session on a real PIC18F16Q20 board, accessible to anyone in the world via the web. Our Supernova USB-to-I3C controller is the device executing every transaction the demo issues.
Try the demo
MEMS sensor evaluation platform.
Our I3C Target Board accessory accepts Bosch's Shuttle 3.0 form-factor and STMicro's DIL24 evaluation boards, the two dominant sockets for I3C-capable sensor prototyping. Drop in your eval board, plug into the Supernova, decode the bus in seconds.
See the I3C Target Board// track record
We've been doing this for years.
Long enough to know where the gotchas live.
// 01 · standards
We help write the spec.
Binho is a MIPI Alliance Contributor Member, actively shaping I3C, the bus the DDR5 sideband is built on.
// 02 · tools
We build the tools.
200+ semiconductor companies use Binho tools to develop, validate, and ship devices with I3C protocol support.
// 03 · plugfests
We prove it in the field.
We've verified our tools at the past 4 MIPI I3C Plugfests, and helped others verify theirs too.
// trusted by engineering teams at
+ hundreds more
Ready to bring up DDR5 SPD over I3C?
From SPD bring-up to production regression, our I3C team knows where this sideband breaks.