// I/Os over I3C Bridge
The bridge spec is new.
Our support is mature.
Binho helps lead the MIPI I/O Bridges Working Group, and built the reference implementation of the spec. The tools and the expertise are here now.
// the specification
An I/O bridge, defined by MIPI.
The MIPI Specification for I/Os Over I3C Bridge defines an I/O bridge as a device that exposes one or more native I/O protocols over a single I3C link, acting as a translator, aggregator, and manager of data and control between a host system and multiple I/O interfaces. Through it, an I3C controller can reach I²C, SPI, UART, and GPIO interfaces without native support for each. It targets designs that route signals across a hinge or joint, such as laptops, foldable phones, and robotics.
The controller discovers the bridge and its capabilities using standard I3C commands, and the bridge raises in-band interrupts to signal when data is ready. The specification is being developed by the MIPI I/O Bridges Working Group, which Binho helps lead.
// how it works
A controller, a bridge, and the devices behind it.
The host runs a single I3C controller, discovers the bridge over standard I3C, and reaches each downstream interface across the same link, with in-band interrupts carrying responses back.
// host side
The I3C controller
A single I3C controller in the host discovers the bridge and its capabilities using standard I3C commands, then reads and writes the interfaces behind it. In-band interrupts let the bridge signal the controller when data is ready.
// the translator
The I/O bridge
The bridge exposes one or more native I/O protocols over a single I3C link. It acts as translator, aggregator, and manager of data and control between the host and the interfaces behind it, so the SoC needs no native support for each one.
// the interfaces
I²C, SPI, UART, GPIO
On its downstream side, the bridge presents native I²C, SPI, UART, and GPIO ports. Each behaves like an ordinary bus of that type, so the interfaces your design already uses simply move behind the bridge.
// the devices
Your off-the-shelf peripherals
The devices on those buses are the same off-the-shelf parts you would wire straight to the processor: sensors, memories, ADCs, port expanders, and more. Nothing about them changes to work behind an I/O bridge. To the device, the bridge is invisible, and it responds exactly as if it were connected directly to the host.
// proven
The reference implementation, built with Microchip and NXP.
At the MIPI Member Meeting in Berlin, the I/O Bridges Working Group ran the bridge on real silicon: an I3C controller reached I²C, SPI, and UART devices through it, every bus captured live. Binho built one of the two controllers, and ran the protocol analysis.
// our edge
We didn't wait for the spec to ship.
Binho's founder, Jonathan Georgino, has co-vice-chaired the MIPI I/O Bridges Working Group since it was formed. We have been inside the spec from day one, building and hardening our tools in step with the standard itself, and proving them through the working group. The tools mature alongside the specification, not after it.
// the tools
Develop and verify with our I3C tools.
Bring up and drive a bridge with the Supernova as your I3C controller, and verify every transaction against the specification with the I3C Analyzer.
Software · Saleae Plugin
I3C Protocol Analyzer Plugin
Decode it as the spec.
The I3C Protocol Analyzer plugin decodes the controller-to-bridge traffic in the context of the I/Os over I3C Bridge specification, so you read bridge transactions, not just raw I3C. It runs inside the Saleae Logic tool your team already uses.
- Decodes in the context of the bridge spec
- I3C timing underneath: DAA, CCCs, IBI, PEC
- Runs in Saleae Logic 1.x and 2.x
Hardware · USB Host Adapter
Binho Supernova
Drive the bridge.
The Supernova is the I3C controller you use to bring up and exercise a bridge: run discovery, configure it, and read and write the I²C, SPI, UART, and GPIO devices behind it. Script it from a GUI, Python, or C.
- Acts as the I3C controller on the bus
- Scriptable from a GUI, Python, or C
- Runs bridge discovery, config, and read/write
// track record
We've been doing this for years.
Long enough to help shape what comes next.
// 01 · standards
We help write the spec.
Binho is a MIPI Alliance Contributor Member, actively shaping I3C and the emerging I/O Bridges specification built on top of it.
// 02 · tools
We build the tools.
200+ semiconductor companies use Binho tools to develop, validate, and ship devices with I3C protocol support.
// 03 · plugfests
We prove it in the field.
We've verified our tools at the past 4 MIPI I3C Plugfests, and helped others verify theirs too.
// trusted by engineering teams at
+ hundreds more
// faq
Common questions.
What is the MIPI I/Os over I3C Bridge?
It is an emerging MIPI Alliance specification that standardizes the encapsulation and packetization of I²C, SPI, UART, and GPIO over a single two-conductor I3C bus. It gives the industry a standard way to aggregate protocols and I/Os onto a minimal number of conductors, so they can pass through tight joints, as in laptops, foldables, and physical AI, without compromising on capabilities or performance.
When will the specification be released?
The MIPI I/O Bridges Working Group is finalizing the specification. Expect an announcement from the MIPI Alliance in Q1 2027 with more detail. Binho has contributed from day one, so our tools track the specification as it advances.
Can I develop and test I/Os over I3C today?
Binho’s tools are ready today. While the specification is still under development, these capabilities are available only to MIPI Alliance Contributor Members. Our I3C Protocol Analyzer plugin and the Supernova are ready now, and once the specification is adopted they will be available for widespread use.
Explore the Supernova What interfaces can a bridge carry?
The initial version of the I/Os over I3C Bridge specification standardizes I²C, SPI, UART, and GPIO, and future versions may add support for additional interfaces. Ordinary off-the-shelf devices on those buses work unchanged behind the bridge, so the interfaces your design already uses simply move behind it.
Why bridge I/Os over I3C instead of wiring each bus separately?
Carrying one I3C link instead of separate wiring for each interface means fewer conductors through tight spots like a hinge or a harness, which is why it fits foldables, wearables, and robotics. It also means fewer controller pins, simpler routing, and one consistent way to manage everything on the bus.
Is Binho involved in the standard itself?
Yes. Binho’s founder co-vice-chairs the MIPI I/O Bridges Working Group, and Binho built one of the I3C controllers and ran the protocol analysis for the working group’s Berlin demonstration.
Read about the Berlin demoBuild it on proven tools.
Drive it with Supernova, decode it with our I3C Analyzer.